DAL, D. And Mansouri, N. 2007. A High-Level Register Optimization Technique for Minimizing Leakage and Dynamic Power. 17th Great Lakes Symposium on VLSI , (Stresa, Italy), 517-520.

DAL, D., & Mansouri, N., (2007). A High-Level Register Optimization Technique for Minimizing Leakage and Dynamic Power . 17th Great Lakes Symposium on VLSI (pp.517-520). Stresa, Italy

DAL, Deniz, And Nazanin Mansouri. "A High-Level Register Optimization Technique for Minimizing Leakage and Dynamic Power," 17th Great Lakes Symposium on VLSI, Stresa, Italy, 2007

DAL, Deniz And Mansouri, Nazanin. "A High-Level Register Optimization Technique for Minimizing Leakage and Dynamic Power." 17th Great Lakes Symposium on VLSI , Stresa, Italy, pp.517-520, 2007

DAL, D. And Mansouri, N. (2007) . "A High-Level Register Optimization Technique for Minimizing Leakage and Dynamic Power." 17th Great Lakes Symposium on VLSI , Stresa, Italy, pp.517-520.

@conferencepaper{conferencepaper, author={Deniz DAL And author={Nazanin Mansouri}, title={A High-Level Register Optimization Technique for Minimizing Leakage and Dynamic Power}, congress name={17th Great Lakes Symposium on VLSI}, city={Stresa}, country={Italy}, year={2007}, pages={517-520} }