Design and hardware implementation of bit length adjustable cosine and sine generator with CORDIC algorithm in FPGA Bit Uzunluğu Ayarlanabilir Kosinüs ve Sinüs Üretecinin CORDIC Algoritması Kullanarak Tasarlanması ve FPGA'de Donanımsal Olarak Gerçeklenmesi

ÖZKILBAÇ B., KARACALI T.

12th International Conference on Electrical and Electronics Engineering, ELECO 2020, Bursa, Türkiye, 26 - 28 Kasım 2020, ss.145-149 identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Cilt numarası:
  • Doi Numarası: 10.1109/eleco51834.2020.00013
  • Basıldığı Şehir: Bursa
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.145-149
  • Atatürk Üniversitesi Adresli: Evet

Özet

© 2020 Turkish Chambers of Electrical Engineers.Today, the need for hardware architectures with fast calculation, high usage area efficiency and accuracy are increasing in digital systems. Therefore, the algorithm used for the hardware to be designed and the number format in which this algorithm operates are quite important. In this study the hardware that calculates the cosine and sinus trigonometric functions commonly used in digital applications is designed in FPGA with Coordinate Rotation Digital Computer (CORDIC) algorithm which combines the three feature mentioned. The designed hardware operates in a two-complement signed integer format and the bit length is adjustable by the user. Thus, a design with the advantages of high speed and usage area efficiency as well as flexibility has been created. Simulation and implementation of the design is done for the Xilinx Artix-7 FPGA model in Vivado software.