Design and Analysis of Parameterized Signed Booth’s Multiplier in FPGA

Özkılbaç B., Karacalı T.

ISASE2021, Erzurum, Türkiye, 7 - 08 Nisan 2022, ss.526-529

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Basıldığı Şehir: Erzurum
  • Basıldığı Ülke: Türkiye
  • Sayfa Sayıları: ss.526-529
  • Atatürk Üniversitesi Adresli: Evet

Özet

Since digital signal processing applications are mostly consist of multiplication and addition operations, multiplication unit is the heart of the digital systems. Therefore, the speed of the multiplication operation is very important for the performance of the system. Digital hardware designers have developed various algorithms to increase the speed of multiplication. Booth's multiplier is an algorithm with highspeed performance and usage area efficiency. In this study, the bit length parameterizable Booth's multiplier circuit was designed using VHDL in FPGA. Synthesis of the designed circuit was carried on Xilinx Artix-7 FPGA chip for 4, 8, 16, 32 bits multipliers and reports of total delay and usage area were obtained. For verification of the design, the behavioral simulation was done in the Xilinx ISE Design Suite 14.6 tool.